1. Field of Invention
This invention relates to an integrated circuit (IC) fabricating process and related structures, and more particularly to a forming method and a structure of a porous low-k layer, an interconnect process and an interconnect structure.
2. Description of Related Art
As the linewidth of IC devices is unceasingly reduced, the affect to the RC delay effect to the speed of the devices continuously becomes larger. One way to reduce the RC delay effect is to decrease the parasite capacitance in the interconnect structure, and the parasite capacitance may be decreased by decreasing the dielectric constant of the dielectric layers in the interconnect structure, i.e., by forming the dielectric layers from a low-k material that has a dielectric constant lower than that (≈4.0) of silicon oxide.
Currently, the low-k materials frequently used include organic low-k materials, porous low-k materials and so on, wherein a porous low-k material may be formed with a sol-gel method, a spin-on method or a chemical vapor deposition (CVD) method that usually uses a framework precursor for forming the framework of the porous structure and a porogen (or a porogen precursor). The porogen will be removed after the porous low-k layer is formed.
Though the dielectric constant of a porous low-k layer can be lower below 2.0, a porous low-k layer easily causes a undesired etching profile possibly because of its low density as compared with non-porous materials and the resulting etching rate difference between the porous low-k layer and the adjacent films. For example, a porous low-k layer may cause an undesired etching profile in an etching step for forming a damascene opening in a damascene process, as shown in FIG. 1.
Referring to FIG. 1, in the damascene process, a porous low-k layer 120 and a hard mask layer 130 are sequentially formed on a substrate 100 having thereon a conductive layer 110 to be connected. A via hole 140 is then formed in the hard mask layer 130 and the porous low-k layer 120 through anisotropic etching, and then the via hole 140 is filled with a conductive material to form a conductive plug (not shown). Possibly because the etching rate difference between the porous low-k layer 120 and the non-porous hard mask layer 130 is large, a kink profile 132 easily occurs to the hard mask layer 130 around the via hole 140. The kink profile 132 will interfere with the filling of the conductive material later, so that the quality of the resulting is lowered.
Moreover, when a cap layer is disposed under the porous low-k layer and the damascene opening has to be formed through the cap layer, a kink etching profile also occurs to the cap layer. Referring to FIG. 4, a damascene opening 440 exposing a portion of the conductive layer 410 to be connected is formed through a hard mask layer 430, a porous low-k layer 420 and a cap layer 415 on the substrate, wherein the cap layer 415 has a kink profile 417 and the hard mask layer 430 has a kink profile 432. The two kink profile 417 and 432 both interfere with the filling of the conductive material.